1. Field of the Invention
The present invention relates to a method for reproducing a printed circuit board (PCB) for semiconductor packages including poor quality PCB units and a method for fabricating semiconductor packages using the reproduced PCB. More particularly, the present invention relates to a method for reproducing a PCB strip for semiconductor packages having a plurality of PCB units including at least one poor quality PCB unit, wherein the poor quality PCB unit is replaced with a normal quality one, thereby achieving a reduction in the amount of package materials used and an improvement in the process efficiency. The present invention also relates to a method for fabricating semiconductor packages using the above PCB strip reproduction method.
2. Related Art
Generally, PCBs are circuit boards mounted with electronic circuits such as semiconductor chips. Such PCBs are fabricated by forming strip-shaped thin conductive lines (conductive traces), which are to be electrically connected to input/output pads of, for example, a semiconductor chip, on a rigid or flexible insulating plate using a printing, plating or etching technique. In accordance with the arrangement of conductive lines, PCBs are classified into a one-sided type, a double-sided type and a multilayered type.
Such PCBs use a substrate comprised of a resin insulating plate coated with a conductive metal thin film. The coating of the conductive metal thin film is carried out using an etched foil method, in which a circuit pattern consisting of conductive traces is formed using an etching process, or an additive method, in which a conductive metal thin film is plated on a selected portion of the resin insulating plate where conductive traces are to be formed, thereby forming a circuit pattern.
Where PCBs are used, high density and high reliability of circuit lines are expected. In this regard, such PCBs sufficiently satisfy requirements for integrated circuits (IC) and large scale integrated circuits (LSI) using a large number of input/output terminals. For this reason, PCBs are widely used for a variety of semiconductor packages such as ball grid array packages, pin grid array packages and chip size packages.
Since the above-mentioned semiconductor packages, which use PCBs, have the same basic structure, the following description will be made in conjunction with only semiconductor packages of the ball grid array type which is a typical type for semiconductor packages. Ball grid array semiconductor,packages are semiconductor packages which have a structure typically including a PCB, at least one semiconductor chip mounted on the upper surface of the PCB, and an array of solder balls disposed on the surface of the PCB opposite to the surface attached with the semiconductor chip and adapted to transfer input and output signals associated with the semiconductor chip. Such ball grid array semiconductor packages are mainly used for multi-pinned devices having 200 pins or more, integrated circuits of very large scale integration (VLSI) and microprocessors.
FIG. 5 is a sectional view illustrating a typical ball grid array semiconductor package.
As shown in FIG. 5, the ball grid array semiconductor package, which is denoted by the reference numeral 1, includes a PCB 11a comprised of a resin substrate 18. A plurality of upper and lower conductive traces 13 are formed on the upper and lower surfaces of the resin substrate 18, respectively. The upper and lower conductive traces 13 are electrically connected through via holes 14. Upper and lower solder masks 19 are formed on the upper and lower surface of the PCB 11a, respectively. The upper solder mask is arranged on the outer portion of the upper surface of the PCB 11a except for the finger portions of the upper conductive traces. The lower solder mask is arranged on the entire lower surface of the PCB 11a except for solder ball pads adapted to fuse solder balls 40. However, the arrangements of the solder masks 13 are not limited to the above-mentioned case. The PCB 11a has a chip mounting region 12 at its central portion. At the chip mounting region 12, the PCB 11a is also provided with a plurality of through holes 12a adapted to easily discharge heat generated during the operation of the semiconductor chip 30. The through holes 12a also serve as ground or power via holes for the semiconductor chip 30. However, the provision of the throughout holes 12a is optional. At the chip mounting region 12, the resin substrate 18 may be exposed or coated with a metal thin film having a desired pattern.
The fabrication of the ball grid array semiconductor package 1 having the above-mentioned structure is carried out as follows. That is, the semiconductor chip 30 is first mounted on the central portion of the PCB 11a corresponding to the chip mounting region 12 by means of a silver-filled epoxy resin 33 which is an adhesive exhibiting a superior thermal conductivity (semiconductor chip mounting step). Thereafter, bond pads (not shown) of the mounted semiconductor chip 30 are electrically connected to the conductive traces 13 formed on the PCB 11a by bonding wires 31 (wire bonding step). A resin encapsulate 32 is then molded on the PCB 11a to protect the semiconductor chip 30 and bonding wires 31 from the environment (resin seal molding step). A plurality of solder balls serving as input/output terminals are then fused on the lower surface of the PCB 11a (solder ball fusing step). The solder balls 40 are electrically connected to the bond pads of the semiconductor chip 30, respectively. Although FIG. 5 illustrates the case having a simple PCB configuration in which one PCB sheet is used, a multilayer PCB configuration may be used which uses a plurality of laminated PCB sheets to obtain an increased solder ball density per unit area.
The PCB 11a, which is used to fabricate a ball grid array semiconductor package, is available from a PCB strip. Such a PCB strip is illustrated in FIG. 6. As shown in FIG. 6, the PCB strip, which is denoted by the reference numeral 10, has a plurality of PCB units 11 arranged on a single plane in the form of a strip. After the completion of the solder ball fusing step, the PCB units 11 of the PCB strip 10 are cut along the cut lines 16 so that they are separated from one another, thereby producing individual semiconductor packages 1. This step is called a "singulation step".
Each PCB unit 11 is defined with a chip mounting region 12 at the central portion of its upper surface. Each PCB unit 11 is also provided at its upper surface with a plurality of conductive traces 13 respectively having via holes 14. The conductive traces 13 are arranged around the chip mounting region 12. The conductive traces 13 are plated with gold or silver at their inner portions (that is, finger portions) to achieve an easy wire bonding to the bond pads of a semiconductor chip mounted on the PCB unit 11. Optionally, heat-discharging through holes 12a are formed in the portion of the PCB unit 11 corresponding to the chip mounting region 12. In FIG. 6, the thin broken line 15 indicates a resin encapsulate molding region where a resin encapsulate is molded whereas the thick broken line indicates a singulation line 17 along which semiconductor packages, obtained after the completion of the resin encapsulate molding and solder ball fusing steps, are cut so that they are separated from one another. Generally, singulation-assistant holes 17a are provided at the four corners of each singulation line 17 which has a square shape. The PCB strip 10 is also provided at both side portions thereof with slots 17b for receiving feeding pins, respectively. By virtue of such slots 17b, the PCB strip 10 can be accurately fed along a required process line while being easily fixed at an accurate processing position. An anti-bending slot 17c is formed in the PCB strip 10 between adjacent PCB units 11. The anti-bending slot 17c serves to prevent the PCB strip 10 from being permanently bent under high temperature and/or high pressure conditions involved in the resin adhesive curing, wire bonding and molding processes.
The reason why such a PCB strip is used in the fabrication of ball grid array semiconductor packages is to improve the process efficiency in the fabrication of semiconductor packages. The use of such a PCB strip enables an accurate feeding of semi-processed products to accurate positions for required processes and a simultaneous and multiple processing for a plurality of PCB units. For this reason, in the manufacture of semiconductor packages, the process flow thereof is conducted for every PCB strip.
Where such a PCB strip is used for the fabrication of ball grid array semiconductor packages, it is necessary to check individual PCB units of the PCB strip in order to find poor quality PCB units involving a short circuit or a degraded appearance. Such poor units should be distinguished from good units by marking those poor units with a particular sign so as to prevent the poor units from being mounted with expensive semiconductor chips or from being subjected to the wire bonding process. Practically, the rate of poor quality PCB units in one PCB strip is relatively high. Where only the good PCB units are subjected to the processes for the fabrication of semiconductor packages, it is possible to reduce the manufacturing costs.
However, poor quality PCB units or semi-processed product units involving a degradation during the processing thereof are processed along with good quality PCB units or semi-processed product units involving no degradation, until the fabrication of semiconductor packages is completed. As a result, the waste of package materials and processing efforts occurs. Poor quality semiconductor packages resulting from such poor quality PCB units or semi-processed product units are sorted only after the fabrication of semiconductor packages is completed. However, this sorting is also troublesome. This work rather results in a reduction in the throughput and productivity of semiconductor packages.